Many electronic products, such as computers, require accurate timing circuits to ensure that particular functions and operations are carried out at a specified time. In this regard, a key feature of many electronic products is a timing circuit that utilizes one or more accurate clock signals.
Typically, an accurate and reliable clock signal is difficult to guarantee, as the timing of clock circuits is known to vary with parameters, such as voltage, temperature, etc. Thus, many such products incorporate a clock failure detection circuit to detect when a clock signal fails. Such a failure may manifest itself by the clock producing irregular pulses, or by remaining too long at a particular high or low voltage level. Alternatively, the frequency of the clock signal (clock rate) may drift outside of tolerable limits. In such a situation, it is important to quickly detect such a malfunction, and implement a mechanism to correct the failure.
U.S. Pat. No. 5,946,362 describes a digital ‘synchronous’ circuit detecting a received clock frequency that is lower than a specified minimum value. The circuit described in U.S. Pat. No. 5,946,362 comprises a reference clock generator and a mechanism to compare clock edges of a generated clock signal with comparable clock edges of the reference clock signal. The circuit operates by counting clock edges of both the clock signal and the reference clock signal, and after a suitable lengthy period, a comparison of the counter values of the two clock signals is performed, to determine whether the generated clock signal is misaligned from the reference clock signal by an amount that is lower than a specified minimum error.
U.S. Pat. No. 5,828,243 describes a digital asynchronous system for detecting whether a received clock frequency matches a specified clock frequency. U.S. Pat. No. 5,828,243 discloses a clock failure detection circuit that monitors a clock by comparing the clock to at least one delayed version of itself is provided. The original clock and the delayed version will be offset, such that an edge of one of either the original clock or the delayed version can clock a logic circuit to determine if the clock is at the correct level. By setting up the delay so that a clock edge is generated when the clock signal should be low, for instance, an output signal in error will be provided whenever the clock is high. Thus, this error could be caused by the clock being stuck high, or by an irregular pulse width.
Basically, the same technique is applied in U.S. Pat. No. 5,828,243 as is performed in U.S. Pat. No. 5,946,362, albeit that an internal high frequency reference clock is not needed in U.S. Pat. No. 5,828,243 as it is an ‘asynchronous’ system (versus the ‘synchronous’ operation of U.S. Pat. No. 5,946,362). In this regard, an asynchronous system may be distinguished from a synchronous system in that the decision of a clock failure (or clock error) and any subsequent clock reset operation is not dependent upon a reference clock.
Thus, the known prior art techniques require a significant delay before a clock error can be determined, i.e. sufficient to enable counters incremented over multiple clock pulses to reach a particular value and a comparison of the counter values used to highlight that respective values are unequal. Furthermore, the known prior art techniques teach monitoring whether a clock signal has fallen below a specified clock rate.
Thus, a need exists for an improved clock failure detection circuit, associated microcontroller system and method of operation therefor.